TransEDA Joins HyperTransport Technology Consortium and Introduces HyperTransport Verification Suite

First Comprehensive Functional Model and Property Library For HyperTransport Help Enable Faster System Verification

LOS GATOS, Calif.--(BUSINESS WIRE)--March 18, 2002-- TransEDA® PLC, the leader in ready-to-use verification solutions for electronic designs, announced that it has joined the HyperTransport(TM) Technology Consortium. As its first deliverable as a Consortium member, the company will offer the new TransEDA HyperTransport Verification Suite(TM) consisting of a HyperTransport bus functional model (BFM) and a HyperTransport property library. The HyperTransport Technology Consortium is an active forum of companies developing advanced interconnect technology that is designed to greatly improve performance of a wide range of communications, storage and networking devices.

"With its excellent reputation for high quality models, TransEDA will be a valuable member of the Consortium," said Gabriele Sartori, president of the HyperTransport Technology Consortium. "There has been a significant amount of demand from other members of the Consortium for bus functional models based on the HyperTransport standard. The new products from TransEDA will help companies developing systems with HyperTransport interfaces to greatly speed their verification process."

HyperTransport Bus Functional Model Speeds Complex System Verification

Using TransEDA's self-checking and automated BFM, verification engineers can verify the HyperTransport interface of a design under realistic and concurrent traffic conditions without having to spend months creating and debugging their own models. The HyperTransport BFM is based on the latest HyperTransport I/O Link Specification from the HyperTransport Technology Consortium (version 1.03), and is part of TransEDA's Foundation Models(TM) system-level verification IP library.

As with all Foundation Models, the HyperTransport BFM is user-configurable. It includes a protocol monitor and can be configured as a fully functional HyperTransport Host Bridge (HTHB) or a single-link device. It can be used as a stand-alone model via the transaction-level application-programming interface (API) for easy integration with existing verification environments. The BFM can also be used with TransEDA's VN-Control(TM) application-specific test automation software for a complete system-level verification environment, including automatic test generation from a high-level template and automatic results checking for target applications. Future HyperTransport BFM releases will include tunnel, bridges with and without tunnels, and secondary host bridge functionality.

The model is compatible with leading hardware description language (HDL) simulators through the Verilog PLI. The intelligent features of the new BFM enable high-volume pseudorandom testing and automatic results checking. See the attached list of product features for further details.

"The automatic generation of a high volume of real world traffic, the protocol interface checking and data consistency checking features of our new BFM are of great value to verification engineers," said Scott Winick, director marketing for system verification at TransEDA. "There are no new languages to learn and no complex models or drivers to write. Our HyperTransport Verification Suite enables designers to focus on chip development rather than writing their own models."

HyperTransport Property Library Verifies Protocol Compliance and Coverage

The second component of the HyperTransport Verification Suite is a comprehensive property library describing the HyperTransport specification in terms of both expected and prohibited protocol behaviors. This property library, used with TransEDA's recently announced VN-Property DX(TM) dynamic property checker, helps to ensure that no HyperTransport operating rules were violated during simulation, and provides detailed protocol coverage metrics and reports. The components of the library can also be used as building blocks to create higher-level properties. More information on dynamic property checking can be found at www.transeda.com/vnpropertydx.

About TransEDA Foundation Models

TransEDA's Foundation Models system-level verification IP library features field-proven processor BFMs, standard bus agents, monitors, and properties for use in existing HDL verification environments or with other TransEDA products. In addition to HyperTransport, the library supports PCI, the Intel Pentium® and Intel Itanium processor families and the Vr5464(TM) MIPS® processor from NEC®.

Pricing and Availability

The HyperTransport Verification Suite will be available in April 2002. List price for the HyperTransport BFM begins at $20,000 (U.S.) for a one-year subscription license. List price for the HyperTransport Property Library for use with VN-Property DX begins at $15,000 (U.S.) for a one-year subscription license.

About HyperTransport Technology

HyperTransport Technology is a new high-speed, high-performance, point-to-point link for integrated circuits. HyperTransport provides a universal connection that is designed to reduce the number of buses within the system, provides a high-performance link for embedded applications, and enables highly scalable multiprocessing systems. It was developed to enable the chips inside of PCs, networking, and communications devices to communicate with each other up to 48 times faster than with some existing technologies.

About HyperTransport Technology Consortium

The HyperTransport Technology Consortium is managed by its members. The consortium promotes the common business interests of providers to the networking, telecommunications, computer and high-performance embedded application through the conduct of a forum for the future development and adoption of the HyperTransport specification.

AMD, API NetWorks, Apple Computers, Broadcom, Cisco Systems, NVIDIA, PMC-Sierra, SGI, Sun Microsystems, and Transmeta are the charter members that comprise the Executive Committee of the HyperTransport Technology Consortium.

Companies interested in the HyperTransport specification are invited to join the consortium. Members of the consortium pay annual dues and receive a royalty-free license to HyperTransport IP, gain access to technical documentation and may attend consortium meetings and events. To become a member, visit the consortium Web site at www.hypertransport.org.

About TransEDA

TransEDA PLC (symbol TRA on the Alternative Investment Market in London) develops and markets ready-to-use verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and bus interfaces. TransEDA's design verification software performs application-specific test automation; configurable HDL checking; code and finite state machine (FSM) coverage analysis; dynamic property checking; and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the world's top 20 semiconductor vendors. For more information, visit www.transeda.com or contact TransEDA at 983 University Avenue, Building C, Los Gatos, California 95032 U.S.A., telephone 408/335-1300, fax (408/335-1319, email info@transeda.com.

Note: TransEDA and Verification Navigator are registered trademarks and TransEDA HyperTransport Verification Suite, VN-Control, and VN-Property DX are trademarks of TransEDA. HyperTransport is a trademark of the HyperTransport Technology Consortium. All other trademarks are properties of their respective holders.

Features of TransEDA's Functional Model For the HyperTransport(TM) Bus

• Signaling - parameterized, mixed-direction support for 2,4,8,16,32 bit CAD (Command, Address, Data) width configurations
• Packet Definition - support for CTL signaling to allow control packets to be inserted in the middle of long data packets
• Packet Definition - support for control packets (info, request, response and command field), and data packets (Payload)
• Packet Definition - command field support for posted and non-posted r/w modes
• Packet Definition - command field support for sized and non-sized r/w modes
• Clocking - support for parameterized clock signals up to 800 MHz
• Clocking - support for sync, pseudo-sync and async modes
• Fabric Operation - support for three virtual channels: posted requests, non-posted requests, and responses
• Fabric Operation - support for broadcast messaging
• Fabric Operation - packet insertion to test starvation, maintenance of fairness and avoidance of deadlock conditions
• Interrupts - interrupt handling
• I/O Ordering - internal memory storage that simulates system memory for testing direct memory access (DMA) modes from the HyperTransport device to system memory
• Error Handling - cyclic redundancy check (CRC) insertion

Features of TransEDA's Property Library for HyperTransport(TM)

• Property definitions prepared to HyperTransport I/O Link Specification revision 1.03
• Checks proper CAD, CTL, CLK signaling
• Checks proper reset/initialization signaling and stability
• Checks power management signaling
• Helps verify packet structure is well-formed
• Flow Control - checks transaction and InitID, link sync, requests (sized R/W, broadcast, flush, fence, atomic R/M/W), responses (RdResponse, TgtDone), I/O streams, flow control, routing (acceptance, forwarding, rejection, host bridges, fairness/forward progress)
• Interrupts - checks interrupt handling
• I/O Ordering - checks upstream ordering, host ordering, downstream ordering
• Configuration Accesses - checks configuration cycle types, function and register mapping, HyperTransport technology device header, bridge headers, capability registers, interrupt discovery and configuration capability block, address re-mapping capability block
• System Management - checks command mapping, special cycles, disconnect/reconnect links
• Error Handling - checks error conditions, error reporting
• Clocking - checks clocking mode definitions, receive FIFO, link frequency initialization and selection
• Reset and Initialization - checks system powerup, reset, low-level link init, I/O fabric init, link width init, and link frequency init

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